Why Pine Trail Isn't Much Faster Than the First Atom

Unlocking the Phenom II X2 555: 3.2GHz Quad-Core for $99

Three days before Apple revolutio...wait, that didn't happen. I kid, I kid.

On Monday AMD updated just about all of its processor families with new chips in response to Clarkdale. We got the Athlon II X2 255, Athlon II X3 440, Phenom II X2 555 BE, Phenom II X4 635 and Phenom II X4 910e. All of the chips are in Bench, so if you want to know how they compare have a look - or check out our review.

There are two things I left out of that review that I felt needed following up on. First, let's take the Phenom II X2 555 BE.

If you read my take on the 555 you'll know that I don't really believe it's worth the price. Most users will be better off with a Core i3 530. There is just one exception I failed to mention: some Phenom II X2s can be turned into a Phenom II X4.

The technique is nothing new. Using any AMD chipset motherboard with a SB710 or SB750 South Bridge and proper BIOS support you'll have a feature called Advanced Clock Calibration (ACC). AMD introduced this feature back in 2008 as a way to improve overclocking on Phenom processors by sacrificing some sort of corner case stability for real world frequency headroom.

The Phenom II X2 is nothing more than a Phenom II X4 with two cores disabled. Originally these cores were disabled because of low yields, but over time yields on quad-core Phenom IIs should be high enough to negate the need for a Phenom II X2. This is most likely why AMD removed the Phenom II X2 from its official price list. It's also why the stranger Phenom II derivatives are also absent from AMD's price list. All that's left are Phenom II X4s pretty much.

A Phenom II X4 900 series die: 258mm2, 4-cores and a 6MB L3 cache. Also the basis for the Phenom II X2.

And herein lies the problem for companies that rely on die harvesting for their product line. Initially, the Phenom II X2 is a great way of using defective Phenom II X4 die. Once yields improve however, you've now created a market for these Phenom II X2s and have to basically sell a full-blown Phenom II X4 at a cheaper price to meet that demand. You could create a new die that's a dual-core Phenom II, but that's expensive and pulls engineers away from more exciting projects like Bulldozer. Often times it's easier to just disable two cores and sell the chip for cheaper than you'd like. At the same time you can do your best to discourage your customers from ordering too many. Remove it off the official price list, charge a little more for it, and direct people at a cheaper native alternative - like the Athlon II X2.

The Athlon II X2 die. Two cores are all you get.

AMD's sticky situation is your gain however. While I can't guarantee that all Phenom II X2s can be converted into quad-core chips, I'd say that your chances are probably pretty good at this point if you get a new enough chip. As with any sort of out-of-spec operation, proceed at your own risk. You may risk ending up with nothing more than a dual-core processor or an unstable quad-core. In my case however, my Phenom II X2 555 BE's extra two cores were easily unlocked.

My Socket-AM3 testbed uses Gigabyte's GA-MA790FXT-UD5P motherboard. In its BIOS there's an option for Advanced Clock Calibration. All you need to do is set EC Firmware Selection to Hybrid, and ACC to Auto:

Patiently waiting and a self-initiated reboot later and my CPU was identified as a Phenom II X4 B55 BE. Four cores running at 3.2GHz, just like a Phenom II X4 955 but for $99.

The chip also performs just like a 3.2GHz quad-core Phenom II, because it is one at this point:

Processor	x264 HD 1st Pass	x25 HD 2nd Pass
AMD Phenom II X4 965	72.1 fps	22.2 fps
AMD Phenom II X4 B55	70.6 fps	21.1 fps
AMD Phenom II X2 555	45.2 fps	10.9 fps

Overclocking is affected. With only two cores active my Phenom II X2 555 BE could run at 3.8GHz without any additional voltage. With four cores active, that number drops down to 3.6GHz.

My Phenom II X2 555 BE, with all four cores unlocked, and running at 3.6GHz.

If you're ok with the possibility of this not working at all, a Phenom II X2 555 BE with all four cores active is the absolute best value you can get for $99. AMD would like to charge you $160 for the opportunity, but you can put the savings towards a better video card or a shiny new SSD.

New Westmere Details Emerge: Power Efficiency and 4/6 Core Plans

Today Intel started talking about its ISSCC plans and included in the conference call were some details on Westmere that I previously didn't know. Most of it has to do with power savings, but also some talk about 32nm quad-core Westmere derivatives!

Westmere is Intel’s 32nm Nehalem derivative. Take Nehalem with all of its inherent goodness, add AES instructions, build it using 32nm transistors and you’ve got Westmere.

Westmere's Secret: Power Gated Un-Core

We just recently met the first incarnation of Westmere - Clarkdale, the dual-core processor that’s been branded the Core i3 and Core i5. Later this quarter we’ll meet Gulftown, a six-core Westmere that’ll be sold under the Core i7 label. All of that is old news, now for the new stuff.

With Nehalem Intel started power gating parts of the chip. Stick a power gate transistor in front of the supply voltage to each core and you can effectively shut off power (including leakage power) to the core when it’s not in use. This was a huge step in increasing power efficiency, something that’s evident when you look at Nehalem idle power numbers.

When you shut off a core you need to save the core’s state so that when it wakes back up it knows what to do next. Remember that power down these cores can happen dozens of times in the course of a second. The cores can’t wake up in a reboot state, they need to simply shut off when they’re not needed and wake back up to continue work when they are needed.

In Nehalem the core’s state (what instruction it’s going to work on next, data in its registers, etc...) is saved in the last level cache - L3. Unfortunately this means that the L3 cache can’t be powered down when the cores are idle, because that’s where they store their state information. Take this one step further and it also means that Nehalem’s L3 cache wasn’t power-gated.

In Westmere, Intel has added a dedicated SRAM to store core state data. Each core dumps its state information into the dedicated SRAM and then shuts off. With the state data kept out of the L3 cache, Westmere takes the next logical step and power gates the L3.

Intel lists this dedicated SRAM as a Westmere-mobile feature, there’s a chance it’s not present on the desktop chips. But it makes sense. Without a way of powering down the L3 cache, Westmere would be a very power hungry mobile CPU. Westmere appears to make it mobile-friendly.

Hex and Quad Core Westmere in 2010?

The last bits of information Intel revealed have to do with its high end desktop/workstation/server intentions with Westmere. The 6-core Westmere is a 240mm^2 chip made up of 1.17B transistors:

That’s six cores on a single die, but with 12MB of L3 cache. Remember that Nehalem/Lynnfield have 8MB and Clarkdale has 4MB. Nehalem’s chief architect, Ronak Singhal told me that he wanted to maintain at least 2MB of L3 per core on the die. A 6-core Westmere adheres to that policy.

The chip works in existing LGA-1366 sockets, so you still have three DDR3 memory channels. 6C Westmere does support both regular DDR3 (1.5V) as well as low voltage DDR3 (1.35V). This is particularly useful in servers where you’ve got a lot of memory present, power consumption should be noticeably lower.

The other big news is that Intel will be releasing 4-core variants of Westmere as well. While I originally assumed this would mean desktop and server, Intel hasn't committed to anything other than a quad-core Westmere. These parts could end up as server only or server and desktop.

The table below shows you the beauty of 32nm. Smaller die, more transistors:

CPU	Codename	Manufacturing Process	Cores	Transistor Count	Die Size
Westmere 6C	Gulftown	32nm	6	1.17B	240mm2
Nehalem 4C	Bloomfield	45nm	4	731M	263mm2
Nehalem 4C	Lynnfield	45nm	4	774M	296mm2
Westmere 2C	Clarkdale	32nm	2	384M	81mm2

It also shows that there's a definite need for Intel to build a quad-core 32nm chip. Die sizes nearing 300mm²aren't very desirable. The question is whether we'll see quad-core 32nm in 2010 desktops or if we'll have to wait for Sandy Bridge in 2011 for that.

We’ll find out soon enough.

AMD Reveals More Llano Details at ISSCC: 32nm, Power Gating, 4-cores, Turbo?

After cashing Intel’s check and appearing more competitive than expected against Clarkdale 2010 is like a fresh start for AMD. The news gets better.
Late last year AMD said that before the end of 2010 it would be sampling its first APU (Accelerated Processing Unit) - codenamed Llano. Today AMD is announcing that the first Llano samples, built on Global Foundries 32nm high-k + metal gate, SOI process will be sampling to partners in the first half of this year.

GF's 32nm SOI High-K + MG process will be used with Llano

For those not in the know, Llano is AMD’s first hybrid CPU-GPU with on-die graphics. The graphics core is a derivative of AMD’s DirectX 11 Evergreen lineup (the same lineage as the Radeon HD 5970, 5870, 5850, 5670, 5570, 5450, etc...).

Llano will go up against Sandy Bridge, which seems to have been pushed back to 2011 for volume availability according to Intel’s internal roadmaps. While Sandy Bridge will have graphics on-die, it will still only be DX10 class - AMD will have the feature-set advantage as far as graphics is concerned.

Llano's Features

Today we learn a bit more about the CPU side of Llano. The first chip will be a quad-core processor plus on-die graphics. Each core is Phenom II derived, but there’s no shared L3 cache. So Llano cores look a lot like Athlon II cores. I’m hearing that they may have some architectural tweaks, so performance could be better than present-day Athlon IIs.

At 32nm each core (minus L2 cache) is only 9.69 mm^2 and is made up of over 35M transistors. Each core is paired with its own 1MB L2 cache, meaning the quad-core processor will have a total of 4MB of L2 on-die. AMD expects Llano to run at above 3GHz, which should be more than possible at 32nm given that we’re already at close to 3GHz with the 45nm Athlon II X4.

AMD’s First Power Gated CPU

With Nehalem Intel introduced power gating, a technique that allows a core to be near-completely powered down minimizing leakage current when inactive. This not only reduces idle power but it also enables Intel to use extra TDP to turbo up active cores.

Llano uses power gating as well as a Digital APM Module. AMD doesn’t go into much detail on the digital APM module but I’m guessing we’ll see the same sort of turbo-like functionality out of Llano, including graphics turbo.

AMD also pointed out that Llano uses a “power aware clock grid design”. I couldn’t get much more information out of AMD on this one, other than its expecting a ~2x reduction in clock switching power. Simply distributing the clock to all parts of a modern day microprocessor can take up quite a bit of power, any improvements in efficiency there are very important.

I’ll keep digging to see if I can get any more details on this aspect of Llano.

Final Words

Llano will obviously require a new socket. All AMD is saying is that OEMs will be shipping systems in 2011. It’s unclear if we’ll see anything in the channel before then, but with sampling in the coming months it appears that AMD could be ready for Sandy Bridge when it arrives next year.
AMD isn’t qualifying its 2011 statement with an indication of what quarter to expect systems. Given that the first samples are going out now, I’d expect to see Llano sometime in the first half of 2011 but that’s purely conjecture on my part. Sandy Bridge is scheduled to ship in volume in the first quarter of 2011.

The big questions going forward are 1) how much AMD and Intel are going to scale up its graphics performance on these chips, and 2) how important DX11 support will be to the upcoming APU race.